1. Field of the Invention
The present invention relates to a semiconductor device having an electrode pad for an external connection.
2. Description of the Related Art
In a chip-formed semiconductor device provided on the semiconductor substrate, a so-called probing is carried out for an electrical characteristic inspection, in which a test probe is made to contact an electrode pad provided for the semiconductor device so that electric power and/or signals are supplied to the semiconductor device. In such a semiconductor device, a stress caused by the contact influences an insulating layer as a lower layer of the electrode pad of aluminum when the test probe is pushed against the surface of the electrode pad, so that a crack is sometimes generated in the insulating layer. The crack deteriorates the insulation of a wiring circuit provided under the lower layer and causes a leakage. As a result, the reliability of the semiconductor device reduces. It is difficult to recognize the crack and to regard the semiconductor device as a defective device only by observing the semiconductor device from the surface since the crack is generated in the lower layer of the electrode pad.
In the conventional semiconductor device, the positioning of the test probe on the electrode pad is determined manually, or automatically by an automatic machine to recognize the electrode pad. However, the positioning of the contact is not limited to a specific region of the electrode pad. Therefore, the test probe possibly contacts the almost whole region of the electrode pad due to a fluctuated operation of the operator and the automatic machine. In order to prevent the defect of the wiring circuit in the lower layer of the electrode pad, the wiring circuit is not provided directly under the electrode pad in the conventional semiconductor device. That is, in the conventional semiconductor device, it is tried to prevent the leakage in the wiring circuit even when the crack is generated in the insulating layer as the lower layer of the electrode pad upon the contact of the test probe, so as to secure the reliability of the semiconductor device.
FIG. 3 is a general view of a layout of an electrode pad. Referring to the semiconductor device shown in FIG. 3, for instance, the electrode pads 4 are provided in I/O (input and output) circuit regions 3 that are arranged in the outer periphery of an internal circuit 2 of a semiconductor chip 1. FIG. 1 shows an outline layout of the electrode pad in the conventional semiconductor device. FIG. 2 is a schematic cross sectional view of the semiconductor device along the C-C line in FIG. 1. A multi-layer interconnection structure is provided on the I/O circuit region 3. That is, an element 105 such as a MOS transistor is formed on the semiconductor substrate 101. First to third metal wiring layers 121, 122, and 123 are laminated above the element 105 through first to third interlayer insulating layers 111, 112, and 113, respectively. First to third via-contacts 131, 132, and 133 connect between the MOS transistor and the first to third metal wiring layers 121, 122, and 123. In this example, an electrode pad 4 is formed to have a CUP (Circuit Under Pad) structure that is made from two metal wiring layers as upper and lower layers. A fourth metal wiring layer 124 as a lower layer pad 4D and a fifth metal wiring layer 125 as an upper layer pad 4U are laminated on the multi-layer interconnection structure, a fifth interlayer insulating layer 115 on the fourth interlayer insulating layer 114. A fourth via-contact 134 connects the third metal wiring layer 123 with the fourth metal wiring layer 124, and the fourth metal wiring layer 124 and the fifth metal wiring layer 125 are electrically and mechanically connected each other via a fifth via-contact 135. A surface insulating layer 116 covers the fifth metal wiring layer 125. Here, a part of the surface of the fifth metal wiring layer 125 is exposed in an opening 116a of the surface insulating layer 116, and functions as a pad.
In the conventional electrode pad, in order to prevent the leak beforehand in the insulating layer directly under the electrode pad 4 due to a crack CX generated upon the contact of the test probe TP with the electrode pad 4, the third metal wiring layer 123 as the uppermost layer, which especially easily receives a large influence from the crack, is not provided directly under the electrode pad 4, as shown in FIG. 2 by a chain line. That is, the periphery of the electrode pad 4 is covered with the surface insulating layer 116 by a predetermined width, and the surface of the electrode pad 4 is exposed in the opening 116a provided on the surface insulating layer 116. The test probe TP is made to contact the above-mentioned surface of the exposed electrode pad 4. The third metal wiring layer 123 is not only not provided directly under the region of the surface of the exposed electrode pad 4, but also not provided under a slightly wider region in consideration of manufacturing deviation (the region P in FIG. 2) . Therefore, the region where the third metal wiring layer 123 is provided in the I/O circuit region 3 is shown in FIG. 8B by dots. Thus, the region where the third metal wiring layer 123 is provided in the I/O circuit region 3 is limited to the region in the both end portions in the Y direction of the I/O circuit region 3 and the along the both sides in the X direction of the I/O circuit region 3.
Moreover, a so-called probe flaw (probe trace) is generated on the surface of the electrode pad 4 upon the contact of the test probe TP to the surface of the electrode pad 4 (not shown). Especially, a plurality of the probe flaws are sometimes produced when the test probe is repeatedly made to contact the same electrode pad. If a bonding is carried out to such an electrode pad with the probe flaws to connect an external electrode such as a gold fine wiring and a tape lead, a substantial contact area of an external electrode and the electrode pad is decreased due to the probe flaws on the surface of the electrode pad. The decrease of the substantial contact area causes the reduction of the reliability of the bonding. Furthermore, an alloy of aluminum and gold is formed on a contact surface of the electrode pad in order to bond the gold wire on the electrode pad to aluminum with a supersonic wave. In this case, the contact area is decreased due to the probe flaw, and the bond strength is reduced and the gold wire comes off easily.
Japanese Laid Open Patent Application (JP-P 2002-329742A) discloses a conventional example to solve such reduction of the bonding strength due to the probe flaw. In the conventional example, two kinds of the electrode pads are formed, one is for the test that the test probe is made to contact the pad, and the other is for the bonding. The bonding is carried out on the electrode pad for bonding. Thus, even if the probe flaw is generated on the electrode pad for the test due to the contact with the test probe, the bonding with high strength can be achieved without getting influence of the probe flaw.
It is effective to improve the bonding strength of the electrode pad as show in the above-mentioned conventional example that the electrode pads for the test and for the bonding are provided separately. However, according to the above example, it is inevitable that an area of the semiconductor device occupied by the electrode pads is increased so that the chip area is increased. The increase of the area becomes an impediment to achieve the high integration of the semiconductor device. Especially, in recent years, the number of the electrode pads tends to increase according to a multi-function of the semiconductor device. Therefore, the above-mentioned conventional example is restricted due to increase in the number of the electrode pads and has a difficulty to response to the multi-function of the semiconductor device.
In the conventional electrode pad shown in FIGS. 1 and 2, the third metal wiring layer 123 as a directly under layer metal wiring layer in the I/O circuit region 3 cannot be provided directly under the region of the electrode pad 4. Therefore, the wiring possible area is limited in the I/O circuit region 3. Especially, when the increase of the number of electrode pads according to the multi-function of the semiconductor device, so that the number of the I/O circuit regions increases to reduce the area of the single I/O circuit region. As a result, the wiring possible area is further decreased, and flexibility of wiring design is also reduced in the I/O circuit region, so that a desirable circuit configuration of the I/O circuit region cannot be achieved. Consequently, it is difficult for the high integration of the semiconductor device.